| General
Information |
| Prerequisite: |
ECE 310 required |
| Time and
Place: |
Credit: 0.75 units (3 hours)
2PM--3:30PM, Tuesday and Thursday, 170 EL
2PM--3:15PM, Friday, 169 EL |
| Textbook: |
Mainly class notes |
| References: |
P.Pirsch, Architectures for Digital Signal Processing, John Wiley and Sons, 1998.
K.K. Parhi, VLSI Digital Signal Processing Systems: Design and
Implementation, John Wiley and Sons, 1999.
J. M. Rabaey, Digital
Integrated Circuits, (Ch. 7 and Ch. 11)
Prentice-Hall, 1996.
|
General Information
This course will focus upon the design of DSP and communications systems
in VLSI. The goal of this course is to span entire design hierarchy from
algorithm design to integrated circuit layout using a mix of tools such as
MATLAB (algorithm design), VHDL (architecture), SYNOPSYS (logic), and
CADENCE (circuit). Automated synthesis and place& route tools (SYNOPSYS
and CADENCE) will be employed extensively so that the design emphasis in
this course will be at the algorithmic
and architectural levels.
Topical Outline
|
1.
|
Algorithm
Design
|
Hours: 15
|
|
Course
overview; DSP
representations
(data- and control-flow graphs, signal-flow graphs, block diagrams); fixed-point DSP design (A/D precision, coefficient quantization, round-off and scaling);
filter structures (recursive, non-recursive and lattice); algorithmic simulations of DSP systems in C and
MATLAB; behavioral modeling in VHDL.
|
| 2. |
Architecture Design
(Algorithm Transforms) |
Hours: 15 |
|
Fast filtering algorithms (Winograd's, Short-length
FIR); retiming
pipelining; block processing;
folding; distributed arithmetic architectures; VLSI performance measures (area, power and speed); structural modeling in
VHDL.
|
| 3. |
DSP Building
Blocks |
Hours:
15 |
|
Arithmetic unit
architectures (adders, multipliers, dividers); bit-parallel; bit-serial; digit-serial;
carry-save
architectures;
redundant number system; modeling for synthesis in VHDL; synthesis via
SYNOPSYS; place-and-route via CADANCE.
|
Grading
The grade will be based upon:
(1) homework (20%)*,
(2) 1 hourly exam (15%),
(3) final exam (20%),
(4) 3-part project,
presentation
and report (45%).
*Note: Homework submissions due
before 5:00PM on the due day. 20% reduction per day for late submissions.
Last updated on: Wednesday, December 01, 1999
|
