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The VLSI Information Processing Systems (ViPS) Research Group established in
1995 at the University of Illinois led by
Prof. Naresh R. Shanbhag focuses on the design of integrated circuits
and systems for communications. Research is classified into the following
areas:
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Communication IC
Design: Research in this area focuses on the design of
low-power, high-performance VLSI architectures and integrated circuit
implementations of broadband communication systems. These projects are
heavily influenced by next generation communication standards.
Projects include: LDPC and turbo decoders, hard and soft-decision
Reed-Solomon decoders, MIMO detectors, wireless and VDSL receivers.
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Communications-Inspired
IC Design: The focus of this area of research is to exploit
the wealth of results from the area of communication systems to design
reliable and efficient systems-on-a-chip (SOC). In particular, SOCs
are viewed as communication networks subject to numerous
non-idealities inherent in modern nanometer process technologies such
as noise, leakage, process variations, and soft errors. Techniques
such as detection, estimation, equalization and coding are employed to
combat circuit and device level non-idealities for various SOC
sub-systems including computation (datapath, arithmetic units, filters
etc.), communication (busses and point-to-point links), and storage
(memory).
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Fundamental
Bounds on Integrated Circuits: Research activities focus on
determining achievable bounds on energy-efficiency and
throughput of nanometer ICs in the presence of
non-idealities such as noise, leakage and process variations.
Information
Theory is employed to obtain efficiency bounds by vieweing nanometer
ICs as noisy communication networks.
Quotes from the 2001
International Technology Roadmap for Semiconductors (http://public.itrs.net/Files/2001ITRS/Home.htm)
that echo
the vision underlying ViPS research directions set in 1995:
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"Crosscutting
Challenge 5--Error-Tolerance Relaxing the requirement of 100%
correctness for devices and interconnects may dramatically reduce the
costs of manufacturing, verification and test...."
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"Design Robustness. Yield
issues, asynchronous design styles, and communications-centric designs
following network oriented paradigms together imply that SOC design
will more resemble the creation of a large scale communication network
than traditional IC design practice. In such a network, communications
can be assumed to be potentially lossy and nodes may fail. Yet, the
network must still achieve its system requirements for processing
correctness and throughput. Such a mapping of a completely specified
function to an inherently imperfect set of implementation fabrics(s)
will demand a whole new ways of designing, mapping, and controlling at
run-time a fault-tolerant processing and communications fabric."
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