Picture Gallery
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Picture Gallery
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| ViPSees at Play: |
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| From left: Lei Wang, Raj Hegde, Jonathan Ashbrook and Ganesh Balamurugan investigate an IC layout. |
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| From left: Ganesh Balamurugan and Lei Wang test an IC in the ViPS lab. |
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| From left: Naresh Shanbhag, Manish Goel, Raj Hegde and Lei Wang discuss algorithmic issues in communication system design. |
| ICs Designed in ViPS |
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| Coded on-chip interconnect by Srini Sridhara: in 130nm, 1.2V, CMOS process. |
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| LDPC Decoder chip by Mohammad Mansour: 640 Mb/s, n=2048, rate = 1/2, 1.2M transistors, 0.18m, 1.8 V CMOS |
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| MAP Decoder Chip by Seok-jun Lee: 27 Mb/s, 330 mW, 150k trans, 0.18m, 1.8 V CMOS |
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| Mirror IC by Lei Wang; 20k transistors, 0.35 micron, 3.3V CMOS technology. |
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| Twin-transistor IC by Ganesh Balamurugan; 20k transistors, 0.35 micron, 3.3V CMOS technology. |
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| SCM VDSL Receiver IC by Jim Tschanz: 300k transistors, 0.35 micron, 3.3V CMOS technology. |
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| Hermitian Decoder IC by Jonathan Ashbrook; 1.2M transistors, 0.35 micron, 3.3V CMOS technology. |
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| Reconfigurable Multiuser detector IC by Tao Long: 210K transistors, 0.25 micron, 3.3V CMOS technology. |
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| Prediction-based soft DSP IC by Raj Hegde: 10K transistors, 0.35 micron, 3.3V CMOS technology. |