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VLSI Information Processing Systems (ViPS) Research Group |
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The VLSI Information Processing Systems (ViPS) Research Group at the University of Illinois led by Prof. Naresh R. Shanbhag focuses on the design of integrated circuits and systems for signal processing and communications. Our work encompasses communication system design, VLSI architectures, and integrated circuit design. Research topics of interest are:
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Stochastic Networked Computation:
Projects in this area explore the idea of distributed on-chip computation
and communication in order to achieve energy-efficiency and robustness in
nanoscale process technologies. Ideas from stochastic signal processing,
robust estimation theory, VLSI architectures and integrated circuit design
are interwoven in order to design the best-in-class computing systems of
the future. Research topics include: design of algorithms,
architectures, integrated circuits, communication fabrics, as well as the
development of models for enabling robust system design. Filtering,
on-chip busses, CDMA PN-code acquisition, motion estimation, DCT, FFT, Viterbi and LDPC decoders are being studied as prototypical applications
of the stochastic computing paradigm. Projects in this category are funded by DARPA
and SRC via the Gigascale
System Research Center
(GSRC), one of five research centers funded under the Focus Center Research
Program (FCRP), National Science Foundation, TI and Intel.
Faculty collaborators: Douglas Jones, Andrew Singer and Rakesh Kumar. Robust and Energy-Efficient High-Speed Links: The primary goal of our research is to develop a system-aware approach to mixed-signal implementations of high-speed (multi-gigabit) links. System-aware mixed signal design seeks to relax the specifications on the analog and digital circuit blocks thereby facilitating the scaling into nanoscale regimes. We are exploring and exploiting the capability of DSP in conjunction with ECC to reduce power in ADC-based high-speed links for applications in back-plane, I/O, and optical. I/O link specific ECC is being explored in terms of BER performance, latency, encoder and decoder architectures. We are exploring techniques to determine BER-optimal rather than SFDR optimal ADC parameters, and dispersion-tolerant clock-recovery techniques. We will employ ultra low-power DSP techniques based on error-resiliency such as algorithmic noise-tolerance (ANT) on the DSP blocks in the transmitter and receiver. Systematic system optimization techniques will be developed to power-optimally budget the slack in BER generated by the use of ECC across the most power-hungry blocks in the link. Prototype chip design is being planned to study the benefits of our design. These projects are funded by SRC, TI, and Intel. Faculty collaborators: Elyse Rosenbaum, Andrew Singer, Jose Scutt-Aine |
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| Contact ViPS at: |
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Naresh R.Shanbhag, Professor Department of Electrical and Computer Engineering Coordinated Science Laboratory University of Illinois at Urbana-Champaign
1308 West Main Street Email: shanbhag@illinois.edu |
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Created and maintained by N. Shanbhag (Last Updated on 31 July 2008) |