Publications are classified into the following areas: Communication IC Design, Communication-Inspired IC Design, Fundamental Bounds on Integrated Circuits.

1. A. Singer, N. Shanbhag, and H.-M. Bae, ``Electronic equalization of fiber optic links," International Zurich Seminar on Communications, Zurich , Switzerland , March 12-14, 2008.

2. H.-M. Bae, J. Ashbrook, N. Shanbhag, and A. Singer, “An 11.5 Gb/s MLSE based CDR IC with Dynamic Power-Transient Tolerance,” Proceedings of the 2008 International Solid-State Circuits Conference, February, 2008.

3. A. Singer, N. Shanbhag and H.-M. Bae, “Electronic dispersion compensation: Signal processing for fiber optic links,” IEEE Signal Processing Magazine, (accepted)

4. H.-M. Bae, J. B. Ashbrook, N. R. Shanbhag, and A. C. Singer, “Fast power transient management for OC-192 add/drop networks,” IEEE Journal of Solid-State Circuits, (accepted).

5. H.-M. Bae, J. B. Ashbrook, J. Park, N. R. Shanbhag, A. C. Singer, and S. C. Chopra, “An MLSE receiver for electronic dispersion compensation of OC-192 fiber links,” IEEE Journal of Solid-State Circuits, vol. 41, no. 11, pp. 2541-2554, Nov. 2006. (Recipient of 2006 IEEE Journal of Solid-State Circuits Best Paper Award)

6. H.-M. Bae, J. Ashbrook, J. Park, N. Shanbhag , A. Singer and S. Chopra, “An MLSE receiver for electronic dispersion compensation of OC-192 fiber links,” Proceedings of the 2006 International Solid-State Circuits Conference, pp. 874-883, February, 2006.

7. M. Mansour and N. R. Shanbhag, “A 640-Mb/s 2048-bit programmable LDPC decoder chip,” IEEE Journal of Solid-State Circuits, vol. 41, no. 3, pp. 684-698, March 2006.

8. Seok-Jun Lee , Naresh R. Shanbhag, and Andrew C. Singer , "A 285-MHz MAP decoder in 0.18µm CMOS," IEEE Journal of Solid-State Circuits, vol. 40, no. 8, pp. 1718-1725, August 2005.

9. S.-J. Lee, N. R. Shanbhag and A. C. Singer, ``Area-efficient, high-throughput MAP decoder architectures,” IEEE Trans. on VLSI Systems, vol. 13, no. 8, pp. 921-933, August 2005.

10. J. E. Jaussi, G. Balamurugan, D. R. Johnson, B. Casper, A. Martin, J. Kennedy, N. Shanbhag, R. Mooney, “8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew,” IEEE Journal of Solid-State Circuits, vol. 40, no. 1, pp. 80-88, January 2005.

11. S.-J. Lee, N. R. Shanbhag, and A. C. Singer, ``Switching methods for linear turbo equalization,'' in IEEE International Symposium on Circuits and Systems, pp. 601-604, May 2004, Vancouver, Ca.

12. S.-J. Lee, A. C. Singer, and N. R. Shanbhag, ``Switching LMS linear turbo equalization,'' in IEEE International Conference on Acoustics, Speech and Signal Processing, pp. 641-644, May 2004, Montreal , Ca.

13. A. Arshad, R. Koetter and N. R. Shanbhag, ``Reduced complexity interpolation for soft-decoding of Reed-Solomon codes,” IEEE International Symposium on Information Theory, pp. 385, June 2004, Chicago.

14. A. Arshad, R. Koetter and N. R. Shanbhag, ``VLSI architectures for soft-decoding of Reed-Solomon codes,” International Communications Conference, pp. 2584-2590, June 2004, Paris.

15. M. Mansour and N. R. Shanbhag, ``High-throughput LDPC decoders,” IEEE Trans. on VLSI Systems, vol. 11, no. 6, pp. 976-996, December 2003.

16. M. Mansour and N. R. Shanbhag, ``VLSI architectures for SISO-APP decoders,” IEEE Trans. on VLSI Systems, vol.11, no. 4, pp. 627-650, August 2003.

17. S. Appadwedula, M. Goel, N. R. Shanbhag, D. L. Jones and K. Ramchandran, ``Total system energy minimization for wireless image transmission,” Journal of VLSI Signal Processing, vol. 27, pp. 99-117, 2001. [PDF].

18. D. Sarwate and N. Shanbhag, ``High-speed architectures for Reed-Solomon decoders," IEEE Trans. on VLSI Systems, 2001. [PDF]

19. N. R. Shanbhag and G.-H. Im, "VLSI systems design of 51.84 Mb/s transceivers for ATM-LAN and broadband access," IEEE Trans. on Signal Processing, vol. 46, no. 5, pp. 1403-1416, May 1998. [PDF]

20. N. R. Shanbhag and M. Goel, "Low-power adaptive filter architectures and their application to 51.84 Mb/s ATM-LAN," IEEE Transactions on Signal Processing, May 1997, pp. 1276-1290. [PDF]

21. M. Goel and N. R. Shanbhag, "Dynamic algorithm transforms (DAT): A Systematic approach to low-power reconfigurable signal processing,"  IEEE Transactions on VLSI Systems, vol. 7, no. 4, pp. 463-476, Dec. 1999. [PDF]

22. N. R. Shanbhag, "Algorithms transformation techniques for low-power wireless VLSI systems design," International Journal of Wireless Information Networks, vol. 5, no. 2, pp. 147-171, 1998. [PDF]

ALGORITHMIC

1. R. Abdallah, and N. R. Shanbhag, “Error-resilient Viterbi decoders,” Proceedings of the 2008 International Symposium on Low Power Electronics and Design, Bangalore, India, August 11-13, 2008.

2. G. Varatkar, S. P. Narayanan, N. Shanbhag and D. L. Jones, “Trends in energy-efficiency and robustness of stochastic sensor NOC,” IEEE Great Lakes Symposium on VLSI, Orlando , FL , May 4-6, 2008.

3. S. P. Narayanan, G. Varatkar, D. L. Jones, and N. Shanbhag, “Computation is estimation: Estimation-theoretic IC design improves robustness and reduces power,” Proceedings of IEEE International Conference on Acoustics, Speech and Signal Processing, March 30-April 4, 2008.

4. G. Varatkar, S. P. Narayanan, N. Shanbhag and D. L. Jones, “Variation-tolerant, low-power PN-code acquisition using stochastic sensor NOC,” IEEE International Symposium on Circuits and Systems, Seattle , WA , May 18-21, 2008.

5. N. Shanbhag, S. Mitra, G. D. Veciana, M. Orshansky, R. Marculescu, J. Roychowdhury, D. Jones, and J. Rabaey, “The search for alternative computational paradigms for the post-Silicon era,” IEEE Design and Test of Computers, August 2008. (Invited paper)

6. G. Varatkar and N. Shanbhag , “Error-resilient motion-estimation architecture,” IEEE Transactions on VLSI, (to appear).

7. S. Sridhara, B. Balamurugan, and N. R. Shanbhag, “Joint equalization and coding for on-chip bus communications,” IEEE Transactions on VLSI, vol. 16, no. 3, pp. 314-318, March 2008.

8. S. Sridhara and N. R. Shanbhag, ``Coding for reliable on-chip busses: A class of fundamental bounds and practical codes,” IEEE Transactions on CAD, vol. 26, no. 5, pp. 977-982, May 2007.

9. G. Varatkar, S. P. Narayanan, N. Shanbhag and D. L. Jones, “Sensor network-on-a-chip,” IEEE Symposium on System-on-a-Chip Design, Tampere , Finland , Nov. 19-21, 2007.

10. G. Varatkar, S. P. Narayanan, N. Shanbhag and D. L. Jones, “Variation-tolerant motion estimation architecture,” IEEE Workshop on Signal Processing Systems (SIPS 2007), Shanghai , China , October 17-19, 2007.

11. S. P. Narayanan, G. Varatkar, D. L. Jones, and N. Shanbhag, “Sensor-Networks-Inspired low-power robust PN code acquisition,” Proceedings of the 41th Annual Asilomar Conference on Signals, Systems, and Computers, Nov. 4-7, 2007.

12. M. Zhang, S. Mitra , T. M. Mak, N. Seifert, Q. Shi, K.-S. Kim, N. R. Shanbhag, N. Wang, and S. Patel, “Robust sequential element design with built-in soft-error resilience,” IEEE Transactions on TVLSI, vol. 14, no. 12, pp. 1368-1378, December 2006.

13. G. Varatkar and N. R. Shanbhag, “Energy-efficient motion estimation using error-tolerance,” Proceedings of the 2006 International Symposium on Low Power Electronics and Design, October 2006.  

14. B. Shim and N. R. Shanbhag, ``Energy-efficient soft-error tolerant digital signal processing,” IEEE Trans. on VLSI, vol. 14, no. 4, pp. 336-348, April 2006.

15. S. Sridhara, G. Balamurugan, and N. R. Shanbhag, "Joint equalization and coding for on-chip bus communication", International Conference on Quality Electronic Design (ISQED), 2005, San Jose , CA.

16. S. Sridhara and N. R. Shanbhag, ``Coding for system-on-chip networks: A unified framework,” IEEE Transactions on VLSI, vol. 13, no. 2, pp. 655-667, June 2005.  

17. S. Sridhara and N. R. Shanbhag, “A low-power bus design using joint repeater insertion and coding,” Proceedings of the 2005 International Symposium on Low Power Electronics and Design, pp. 99-102, August 2005.

18. B. Shim, S. Sridhara and N. R. Shanbhag, ``Reliable low-power digital signal processing via reduced precision redundancy,” IEEE Trans. on VLSI Systems, vol. 12, no. 5, pp. 497-510, May 2004.

19. N. R. Shanbhag, ``Reliable and efficient system-on-a-chip design,” Computer Magazine, vol. 37, no. 3, pp. 42-50, March 2004.

20. R. Hegde and N. R. Shanbhag, ``A voltage overscaled low-power digital filter IC,” IEEE Journal of Solid-State Circuits, vol. 39, no. 2, pp. 388-391, February 2004.

21. L. Wang and N. R. Shanbhag, ``Low-power filtering via adaptive error-cancellation,” IEEE Trans. on Signal Processing, vol. 51, no. 2, pp. 575-583, February 2003.

22. R. Hegde and N. R. Shanbhag, ``Soft digital signal processing,” IEEE Trans. on VLSI Systems, vol. 9, no. 6, pp. 813-823, December 2001. [PDF]

CIRCUIT

1. M. Zhang and N. R. Shanbhag, “Dual sampling skewed CMOS design for soft error-tolerance,” IEEE Transactions on CAS II, vol. 53, no. 12, pp. 1461-1465, Dec. 2006.

2. M. Zhang and N. R. Shanbhag, “Soft error-rate analysis (SERA) methodology,” IEEE Transactions on CAD, vol. 25, no. 10, pp. 2140-2155, Oct. 2006.

3. M. Zhang and N. Shanbhag, “A CMOS design style for logic circuit hardening,'' IEEE International Reliability Physics Symposium, pp. 223-229, Apr. 17-21, 2005. (Selected as one of the 'Jewels of IRPS')

4. M. Zhang and N. Shanbhag, “An energy-efficient circuit technique for single event transient noise-tolerance,'' IEEE International Symposium on Circuits and Systems, pp. 636-639, May 23-26, 2005.

5. R. K. Krishnamurthy, A. Alvandpour, G. Balamurugan, N. Shanbhag, K. Soumyanath, and S. Borkar, ``A 130nm 6GHz 256x32b leakage-tolerant register file,” IEEE Journal of Solid-State Circuits, vol. 37, no. 4, pp. 624-632, May 2002.

6. G. Balamurugan and N. R. Shanbhag, “The twin-transistor noise-tolerant dynamic circuit technique,” IEEE Journal of Solid-State Circuits, vol. 36, no. 2, pp. 273-280, Feb. 2001. [PDF]

7. L. Wang and N. R. Shanbhag, ``An energy-efficient noise-tolerant dynamic circuit technique," IEEE Trans. on Circuits and Systems, Part II, vol. 47, no. 11, pp. 1300-1306, November 2000. [PDF]

8. N. R. Shanbhag, K. Soumyanath and S. Martin, ``Reliable low-power design in the presence of deep submicron noise," Tutorial paper in Intl' Symposium on Low-Power Electronics and Design '00, Portofino Coast, Rapallo, Italy. [PDF]

1. L. Wang and N. R. Shanbhag, ``Energy-efficiency bounds for deep submicron VLSI systems in the presence of noise,” IEEE Trans. on VLSI, vol. 11, no. 3, pp. 254-269, April 2003.

2. R. Hegde and N. R. Shanbhag, ``Towards achieving energy-efficiency in presence of deep submicron noise,” IEEE Trans. on VLSI Systems, vol. 8, no. 4, pp. 379-391, August 2000. (Recipient of the 2001 IEEE Transactions on VLSI Systems Best Paper Award) [PDF]

3. R. Hegde and N. R. Shanbhag,"Lower bounds on energy dissipation and noise- tolerance for deep submicron VLSI," 1999 IEEE International Symposium on Circuits and Systems, Orlando, FL. (Recipient of Second Place Prize in Best Student Paper Contest). [PDF]

4. S. Ramprasad, N. R. Shanbhag, and I. N. Hajj, ``A coding framework for low-power address and data busses," IEEE Trans. on VLSI Systems, vol. 7, no. 2, pp. 212-221, June 1999. [PDF]

5. S. Ramprasad, N. R. Shanbhag, and I. N. Hajj, "Information-theoretic bounds on average signal transition activity", IEEE Transactions on VLSI, vol. 7, no. 3, pp. 359-368, Sept. 1999. [PDF]         

6. S. Ramprasad, N. R. Shanbhag, and I. N. Hajj, ``Signal coding for low-power: Fundamental limits and practical realizations," IEEE Trans. on Circuits and Systems, Part II, vol. 46, no. 7, July 1999. [PDF]

7. N. R. Shanbhag, "A mathematical basis for power-reduction in digital VLSI systems", IEEE Trans. on Circuits and Systems, Part II, vol. 44, no. 11, pp. 935-951, Nov. 1997. (Recipient of the 1999 IEEE Leon K. Kirchmayer Prize Paper Award). [PDF]